Generally, one of the driving factors in the design of modern electronics is the amount of computing power and storage that can be shoehorned into a given space. The well-known Moore's law states that the number of transistors on a given device will roughly double every eighteen months. In order to compress more processing power into ever smaller packages, transistor sizes have been reduced to the point where the ability to further shrink transistor sizes has been limited by the physical properties of the materials and processes. Designers have attempted to overcome the limits of transistor size by packaging ever larger subsystems into one chip (systems on chip), or by reducing the distance between ships, and subsequent interconnect distance.
One method used to reduce the distance between various chips forming a system is to stack chips, with electrical interconnects running vertically. This can involve multiple substrate layers, with chips on the upper and lower surfaces of a substrate. One method for applying chips to the upper and lower side of a substrate is called “flip-chip” packaging, where a substrate has conductive vias disposed through the substrate to provide an electrical connection between the upper and lower surfaces. These interposer substrates for flip chips are commonly silicon, glass or some other insulator with copper, gold or other conductors disposed in the vias through the interposer.
The through silicon vias (TSVs) are also used to create 3D integrated circuits, and are advantageous over wire bonding or other connection techniques because it permits a substantially higher density vias in a given amount of space, and because the length of the connections is shorter. A 3D package such as System in Package, Chip Stack Multi-Chip Module (MCM), etc. contains two or more chips (integrated circuits, ICs) stacked vertically so that they occupy less space and/or have greater connectivity. The different dies in the stack may be heterogeneous, e.g. combining CMOS logic, DRAM and III-V materials into a single IC. An alternate type of 3D package is Silicon Carrier Packaging Technology, where ICs are not stacked but a carrier substrate containing TSVs is used to connect multiple ICs together in a package. In most 3D packages, the stacked chips are wired together along their edges and this edge wiring slightly increases the length and width of the package and usually requires an interposer layer between the chips. In some 3D packages, through-silicon vias replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or width. Because no interposer is required, a TSV 3D package can also be flatter than an edge-wired 3D package. This TSV technique is sometimes also referred to as TSS (Through-Silicon Stacking or Thru-Silicon Stacking). A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. By using TSV technology, 3D ICs can pack a great deal of functionality into a small footprint.
Frequently, packages are joined using wire bonding, where a conductive wire is spot welded or soldered to a pad, and then cut and welded to a second pad. Gold is frequently used for both the bonding pads and wires in such a case, primarily due to gold's resistance to oxidation and relatively low welding temperature. Solder ball grid arrays are also a technique sometimes used to joining packages, with an array of solder balls deposited on the bonding pads of a first package, and with a second package joined at its own bonding pad sites to the first pad via the solder balls. The environment with the solder ball grid array is heated to melt the solder balls and the packages compressed to cause the solder balls to contact the pads on both packages.